In lab 4 task 4 you should change the rm and mkdir commands for Makefile compile to:
# rm -r questa_lib
mkdir -p questa_lib
You must also in the terminal write:
export MODELSIM=""
before compile and simulate.
You MUST also i Vivado under "tools" --> "settings" --> "general" set project device to "Board" and "ZCU106 Evaluation Platform" and set target language to "Verilog" BEFORE generating the IP.